1. Field of the Invention
The present invention relates to an apparatus for generating a driving voltage for a sense amplifier, in particular, which has an enhanced ability of generating a core voltage for the sense amplifier.
2. Description of the Prior Art
As well known in the art, a conventional method of reading data stored in a memory cell of a memory device such as DRAM, SDRAM and DDR SDRAM is performed as follows. A word line is primarily enabled to transfer electric charge stored in the memory cell into a bit line. Then, for example, the electric potential of the bit line is transited to a high potential level and the electric potential of a bit line bar is transited to a low potential level by using a sense amplifier, which serves to sense and amplify any minute potential difference between bit lines B/L, /B/L.
In this case, in a case that the potential difference between the bit lines increases more rapidly, the output time through a data output buffer becomes shorter to enable a high speed process of the memory device. In order to enlarge the potential difference between the bit lines in a short time period, the driving voltage of the sense amplifier is necessarily maintained high for a predetermined time period (that is, during sensing). In general, the voltage for driving the sense amplifier is a core voltage (which is typically equal to a voltage value where the data stored in the memory cell is at a high level).
FIG. 1 illustrates the connected relation between a core voltage driver 101 or means for generating a core voltage and a sense amplifier. As shown in FIG. 1, the sense amplifier uses a core voltage VCORE as a driving voltage. The core voltage driver 101 is typically arranged in a peripheral area 100 of a memory device (not shown), whereas the sense amplifier is typically arranged in a core area 120 of the memory device. For reference, the core area 120 includes a memory cell array of the memory device, whereas the peripheral area 100 refers to a portion of the memory device excluding the core area 120.
The operation of the circuit shown in FIG. 1 will be described in reference to FIG. 2 which illustrates an operation waveform of the circuit in FIG. 1.
Referring to FIG. 2, VDD indicates an external power supply, VCORE indicates an output voltage of the core voltage driver, and VBLP indicates a bit line precharge voltage. Also, ACTIVE indicates a signal enabled by a word line, and S/A Enable indicates a signal for enabling the sense amplifier.
As shown in FIG. 2, in the prior art, a bit line voltage temporarily drops to a predetermined value and then rises again while the voltage difference between bit lines is gradually increased by the enabled sense amplifier. As a result, a time delay is caused in a sensing operation.
FIG. 3 is a circuit embodied for solving these problems in the conventional circuit shown in FIG. 1. The circuit in FIG. 3 is arranged in a peripheral area 300 of a memory device, and comprises core voltage step-up drivers 301 and 302, that is, a core voltage step-up driver 301 and a core voltage step-up means 302 for stepping up the core voltage. The circuit in FIG. 3 has parts equal to those of the circuit in FIG. 1 except that the step-up means 302 steps up the core voltage. A sense amplifier is arranged in a core area 320.
As shown in FIG. 3, the core voltage step-up means 302 includes a PMOS transistor between an output node n1 of the core voltage driver and the power supply VDD, which is turned on/off in response to a sense amplifier enable-signal S/A Enable.
The operation of the circuit shown in FIG. 3 will be described in reference to FIG. 4 which is an operation waveform of the circuit shown in FIG. 3.
As shown in FIG. 3, when the PMOS transistor shown in FIG. 3 is turned on in response to the sense amplifier enable-signal S/A Enable during detection amplification, the power supply VDD is applied to the node n1. As can be seen in FIG. 4, this can prevent temporal step-down of a bit line voltage which was observed during detection amplification. (In reference, a range a in FIG. 4 corresponds to an operation range of the core voltage step-up means 302 in FIG. 3.)
However, the circuit shown in FIGS. 3 and 4 has drawbacks in that the core voltage is necessarily overdriven for a short period right after the operation of the sense amplifier thereby increasing power consumption. Also, power noise may occur according to power slopes thereby decreasing stability as well as deteriorating the yield of a wafer.
FIG. 5 illustrates an arrangement of core voltage step-up drivers in use for conventional memory banks. In this illustration, the core voltage step-up drivers 510 and 511 indicate those core voltage step-up drivers shown in FIG. 3. As shown in FIG. 5, two banks 501 and 503 share the core voltage step-up driver 510. Likewise, another two banks 502 and 503 share the core voltage step-up driver 511.
In the arrangement shown in FIG. 5, however, the core voltage step-up driver 510 powers both of the banks 501 and 502 even though only the bank 501 is operated. This creates a problem of consuming a large quantity of power.